publications

2025

2025

1. 

   Circuit Optimization using Arithmetic Table Lookups

   Raghav Malik, Vedant Paranjape, and Milind Kulkarni

   Proc. ACM Programming Language Design and Implementation (PLDI), Jun 2025

   Abs DOI

   Fully Homomorphic Encryption (FHE) is a cryptographic technique that enables privacy-preserving computation. State-of-the-art Boolean FHE implementations provide a very low-level interface, usually exposing a limited set of Boolean gates that programmers must use to write their FHE applications. This programming model is unnecessarily restrictive: many Boolean FHE schemes support programmable bootstrapping, an operation that allows evaluation of an arbitrary fixed-size lookup table. However, most modern FHE compilers are only capable of reasoning about traditional Boolean circuits, and therefore struggle to take full advantage of programmable bootstrapping. We present COATL, an FHE compiler that makes use of programmable bootstrapping to produce circuits that are smaller and more efficient than their traditional Boolean counterparts. COATL generates circuits using arithmetic lookup tables, a novel abstraction we introduce for reasoning about computations in Boolean FHE programs. We demonstrate on a variety of benchmarks that COATL can generate circuits that run up to 1.5\texttimes faster than those generated by other state-of-the-art compilation strategies.

2. 

   Biscotti: An Approach to Parallel Scheduling for Vectorized Encrypted Arithmetic Circuits

   Vedant Paranjape, Aman Gupta, Sreevickrant Sreekanth, and 3 more authors

   2025

   Poster presented at The Midwest Programming Languages Summit (MWPLS), December 2025

   PDF

2023

2023

1. 

   DEEPFAKE CLI: Accelerated Deepfake Detection Using FPGAs

   Omkar Bhilare^*, Rahul Singh^*, Vedant Paranjape^*, and 3 more authors

   In Parallel and Distributed Computing, Applications and Technologies, 2023

   Abs DOI

   Because of the availability of larger datasets and recent improvements in the generative model, more realistic Deepfake videos are being produced each day. People consume around one billion hours of video on social media platforms every day, and that’s why it is very important to stop the spread of fake videos as they can be damaging, dangerous, and malicious. There has been a significant improvement in the field of deepfake classification, but deepfake detection and inference have remained a difficult task. To solve this problem in this paper, we propose a novel DEEPFAKE C-L-I (Classification - Localization - Inference) in which we have explored the idea of accelerating Quantized Deepfake Detection Models using FPGAs due to their ability of maximum parallelism and energy efficiency compared to generalized GPUs. In this paper, we have used light MesoNet with EFF-YNet structure and accelerated it on VCK5000 FPGA, powered by state-of-the-art VC1902 Versal Architecture which uses AI, DSP, and Adaptable Engines for acceleration. We have benchmarked our inference speed with other state-of-the-art inference nodes, got 316.8 FPS on VCK5000 while maintaining 93% Accuracy.

2. 

   Sensor Fusion Devs for Angle Estimation on Inertial Measurement Unit

   Gabriel Wainer, Joseph Boi-Ukeme, and Vedant Paranjape

   In 2023 Winter Simulation Conference (WSC), 2023

   DOI